VHDL-Based Design and Performance Evaluation of a Dadda-Based Floating-Point Multiplier

Abstract

Floating-point multiplication is a core operation in digital signal processing, graphics and scientific accelerators, and its speed is limited chiefly by the multiplication of the two mantissas. This paper presents a VHDL-based design and performance evaluation of an IEEE-754 single-precision floating-point multiplier whose 24×24-bit mantissa product is computed with a Dadda tree. The Dadda reduction scheme minimizes the number of carry-save stages and, unlike the Wallace tree, defers reduction until it is strictly required, which lowers the number of full- and half-adder cells while keeping the logarithmic delay of a tree multiplier. The complete multiplier—sign handling, exponent addition with bias correction, Dadda-based mantissa multiplication, normalization and round-to-nearest—is described structurally in VHDL and made parametric so the same source scales toward double precision. The design was functionally verified against a reference floating-point model, synthesized for evaluation, and compared with array- and Wallace-based multipliers for delay, area and power. The representative results reported here indicate that the Dadda-based multiplier attains the low delay of a Wallace tree while using fewer adder cells, giving a lower area and a lower power–delay product. All numerical values are illustrative and should be reproduced with the reader's own synthesis and simulation data.